a) Field of the Invention
The present invention relates to an electronic circuit device with multi-layer wiring and its manufacture, and more particularly to an electronic circuit device having an interlayer insulating film formed on an insulating film covering the surface of the underlying wiring layer.
b) Description of the Related Art
FIG. 8 is a cross sectional view showing the connection portion between a lower level wiring layer and a higher level wiring layer of a liquid crystal display (LCD) panel with thin film transistors (TFTs).
On the surface of a glass substrate 100, a gate insulating film 101 is formed. In the region where a TFT is formed, a polysilicon film is formed between the glass substrate 100 and gate insulating film 101. In this polysilicon film, a channel region, a source, and a drain region of TFT are formed. Since FIG. 8 shows the connection portion between the lower and higher level wiring layers, the polysilicon film is not shown in this portion.
A gate wiring line 102 of aluminum is formed on the gate insulating film 101. The gate wiring line 102 is patterned at the same time when the gate electrode of TFT is patterned. The surface of the gate wiring line 102 is covered with an anodic oxide film 103 formed through anodic oxidation of aluminum. An interlayer insulating film 104 is formed over the substrate including the surface of the anodic oxide film 103.
A drain wiring line 105 of aluminum is formed on the interlayer insulating film 104. The drain wiring line 105 is deposited and patterned at the same time when the drain electrode of TFT is deposited and patterned. The gate wiring line 102 and drain wiring line 105 are disposed in a lattice shape in the area where pixels are formed. Both the wiring lines are electrically insulated at their cross points by the interlayer insulating film 104. The anodic oxide film 103 improves the insulation reliability between the gate wiring lines 102 and drain wiring lines 105.
In some cases, in an LCD with built-in peripheral circuits, an output signal of one transistor of the peripheral circuit drives another transistor, by connecting the drain wiring line of the one transistor at the preceding stage to the gate wiring line of the other transistor at the succeeding stage.
In connecting the gate wiring line and drain wiring line, a contact hole 106 is formed in the interlayer insulating film 104 and anodic oxide film 103 before the drain wiring layer is deposited. The contact hole 106 in the interlayer insulating film 104 is formed through anisotropic etching.
The anodic oxide film 103 is etched by isotropic wet etching using, for example, chromium mixed acid (CrO.sub.3 .multidot.HNO.sub.3 .multidot.H.sub.3 PO.sub.4 .multidot.CH.sub.3 COOH+nH.sub.2 O), because there is no etching gas having a large etching selection ratio to the gate wiring layer 102. Therefore, the anodic oxide film 103 is side etched, leaving a hollow 107 at the lower side wall of the contact hole 106.
After the contact hole 106 is formed, the drain wiring layer is deposited over the whole surface of the substrate by sputtering or the like. Since the hollow 107 is formed at the lower side wall of the contact hole 106, step coverage of the drain wiring line at the contact hole lowers so that breakage or disconnection of the drain wiring line becomes likely to occur. The anodic oxide film for preventing a short circuit between the gate wiring line and drain wiring line in the region where pixels are formed, makes it difficult to connect the gate wiring line and drain wiring line at the region where peripheral circuits are formed.
As above, although the surface of the gate wiring layer is formed with an anodic oxide film in order to improve the insulation reliability between the gate wiring line and drain wiring line in the pixel forming region, this anodic oxide film lowers the connection reliability between the gate and drain wiring lines in the region where the peripheral circuits are fabricated.